1. Field of the Invention
This invention relates to an active matrix liquid crystal display, and more particularly, to an active matrix liquid crystal display, wherein it is provided with a device for applying a gate pulse to transistors connected to picture elements (or pixels) consisting of a liquid crystal.
2. Description of the Related Art
The conventional active matrix liquid crystal display apparatus displays a picture by controlling the light transmissivity of liquid crystal using an electric field. As shown in FIG. 1, such a liquid crystal display apparatus includes a data driver 12 for driving signal lines SL1 to SLm at a liquid crystal panel 10, and a gate driver 14 for driving gate lines GL1 to GLn at a liquid crystal panel 10. In the liquid crystal panel 10, pixels 11 connected to signal lines SL and gate lines GL are arranged in an active matrix pattern. Each pixel 11 includes a liquid crystal cell C1c for responding to a data voltage signal DVS from the signal line SL to control a transmitted light quantity, and a thin film transistor (TFT) CMN for responding to a scanning signal SCS from the gate line GL to switch the data voltage signal DVS to be applied from the signal line SL to the liquid crystal cell C1c. As the gate lines GL1 to GLn are sequentially driven, the data driver 12 applies the data voltage signal DVS to all the signal lines SL1 to SLm. The gate driver 14 allows the gate lines GL1 to GLn to be sequentially enabled for each horizontal synchronous interval by applying the scanning signal SCS to the gate lines GL1 to GLn sequentially. To this end, the gate driver 14 consists of a shift register 16 responding to a gate start pulse GSP from a control line CL and a gate scanning clock GSC from a gate clock line GCL, and a level shifter 18 connected between the shift register 16 and the gate lines GL1 to GLn. The shift register 16 outputs the gate start pulse GSC from the control line CL to any one of n output terminals QT1 to QTn and, at the same time, responds to the gate scanning clock GSC to shift the gate start pulse GSP from the first output terminal QT1 to the nth output terminal QTn sequentially. The level shifter 18 generates n scanning signals SCS by shifting voltage levels of the output signals of the shift register 16. To this end, the level shifter 18 consists of n inverters 19 that are connected between the n output terminal QT1 to QTn the shift register 16 and the n gate lines GL1 to GLn, respectively, and fed with low and high level gate voltages Vgl and Vgh in a direct current shape from a first and a second voltage line FVL and SVL, respectively. The inverters 19 selectively supply any one of the low and high level gate voltages Vg1 and Vgh to the gate line GL in accordance with a logical state at the output terminal QT of the shift register 16. Accordingly, only one of the n scanning signals SCS has the high level gate voltage Vgh.
In this case, the TFT CMN receiving a scanning signal SCS having the high level gate voltage Vgh from the gate line GL is turned on, and the liquid crystal cell C1c charges the data voltage signal DVS during an interval when the TFT CMN is turned on. The voltage charged into the liquid crystal cell C1c in this manner drops down when the TFT CMN is turned off and therefore becomes lower than a voltage of the data voltage signal DVS. Accordingly, a feed through voltage Vp corresponding to a difference of voltage between the voltage charged in the liquid crystal cell and the data voltage signal DVS, is generated. This feed through voltage )Vp is caused by a parasitic capacitance existing between the gate terminal of the TFT CMN and the liquid crystal cell C1c, which changes a transmitted light quantity at the liquid crystal cell C1c periodically. As a result, a flicker and a residual image are generated at a picture displayed on the liquid crystal panel.
In order to suppress such a feed through voltage )Vp, as shown in FIG. 1, support capacitors Cst are connected, in parallel, to the liquid crystal cells. The support capacitor Cst compensates for the liquid crystal cell voltage when the TFT CMN is turned off, thereby suppressing the feed through voltage )Vp as expressed in the following formula:
xe2x80x83Vp=(Vonxe2x88x92Voff)xc2x7Cgs/C1c+Cst+Cgsxe2x80x83xe2x80x83(1)
in which Von represents a voltage at the gate line GL upon turning on of the TFT CMS; Voff represents a voltage at the gate line GL upon turning off of the TFT CMS; and Cgs represents a capacitance value of a parasitic capacitor existing between the gate terminal of the TFT CMN and the liquid crystal cell. As seen from formula (1), the feed through voltage )Vp increases depending on a voltage difference at the gate line GL upon turning on and turning off of the TFT CMN.
In order to sufficiently suppress the feed through voltage )Vp, a capacitance value of the support capacitor Cst must be increased. This causes aperture ratio of display area to be decreased, so that it is impossible to obtain a sufficient display contrast. As a result, it is difficult to suppress the feed through voltage )Vp sufficiently by means of the support capacitor Cst.
As another alternative for suppressing the feed through voltage )Vp, there has been suggested a liquid crystal display apparatus adopting a scanning signal control system for allowing the falling edge of the scanning signal SCS to have a gentle slope. In the liquid crystal display apparatus of a scanning signal control system, the falling edge of the scanning signal SCS changes in the shape of a linear function as shown in FIG. 2A, an exponential function as shown in FIG. 2B, or a ramp function as shown in FIG. 2C. Examples of such a liquid crystal display apparatus of scanning signal control system are disclosed in the Japanese Patent Laid-Open Gazette Nos. 1994-110035 and 1997-258174 and the U.S. Pat. No. 5,587,722. However, these liquid crystal display devices of a scanning signal control system additionally require a circuit modification of the gate driver or a new waveform modifying circuit to be positioned between the gate driver and each gate line at the liquid crystal panel. The gate driver described in the U.S. Pat. No. 5,587,722 has a complex circuitry and consumes a great amount of power, because a circuit allowing the falling edge of the scanning signal to be stepwise is formed in a gate driver chip.
For example, as shown in FIG. 3, the liquid crystal display apparatus of a scanning signal control system disclosed in the Japanese Patent Laid-Open Gazette No. 1994-110035 includes an integrator 22 connected between a scanning driver cell 20 and a gate line GL. The integrator 22 consists of a resistor R1 between the scanning driver cell 20 and the gate line GL, and a capacitor C1 connected between the gate line GL and the ground voltage line GVL. The integrator 22 integrates a scanning signal SCS to be applied from the gate driver cell 20 to the gate line GL, thereby changing the falling edge of the scanning signal SCS into a shape of exponential function. A TFT CMN included in a pixel 11 is turned on until a voltage of the scanning signal SCS from the gate line GL drops less than its threshold voltage. At this time, an electric charge charged in a liquid crystal cell C1c is pumped into the gate line GL through Cgs. However, sufficient electric charge is charged into the liquid crystal cell C1c by means of a data voltage signal DVS passing through the TFT CMN from a signal line SL. As a result, the voltage charged in the liquid crystal cell C1c does not drop. Then, since a voltage variation amount in the gate line GL is a maximum threshold voltage of the TFT CMN when a voltage of the scanning signal SGS at the gate line GL drops less than a threshold voltage of the TFT CMN, electric charge amount pumped from the liquid crystal cell C1c into the gate line GL becomes very small. As a result, the feed through voltage )Vp can be suppressed sufficiently.
In the liquid crystal display apparatus of a scanning signal control system as described above, since the feed through voltage )Vp is sufficiently suppressed to reduce a flicker and a residual image considerably but a waveform modifying circuit, such as an integrator, for each gate line must be added, the circuit configuration thereof becomes very complex. Further, because the rising edge of the scanning signal also changes slowly due to the waveform modifying circuit, a charge initiation time at the liquid crystal cell is delayed.
Meanwhile, the U.S. Pat. No. 5,587,722 discloses a shift register 3 selectively receiving power supply voltages VVDD and VVDDxc2x7R1/(R1+R2), as shown in FIG. 4. The shift register 3 responds to the supply voltages VVDD and VVDDxc2x7R1/(R1+R2) and generates a stepwise pulse. However, the shift register 3 must be driven at a high voltage because the supply voltage VVDD is equal to a high-level gate voltage to be applied to gate lines on the liquid crystal display panel. In other words, inverters 5, 6 and 9 included in the shift register 3 operate at about 25 V of the driving voltage, if maximum voltage for turning on the TFT is a voltage of 2.5. Due to this, the active matrix liquid crystal display apparatus, disclosed in U.S. Pat. No. 5,587,722, consumes a large amount of power.
Accordingly, it is an object of the present invention to provide a liquid crystal display apparatus and method that is adapted to eliminate flickering and residual images as well as to simplify the circuit configuration thereof.
Additional features and advantages of the invention will be set forth in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
In order to achieve this and other objects of the invention, a liquid crystal display apparatus according to one embodiment of the present invention includes a plurality of pixels including switching transistors, each switching transistor having an electrode connected to a pixel electrode and a gate electrode; a plurality of data signal lines connected to the electrode associated with any one of the transistors; a plurality of gate signal lines connected to the gate electrode associated with any one of the transistors; and a gate driver connected to the plurality of gate signal lines. The gate driver receives first and second voltages and outputting at least one of the first and second voltages in such a manner to sequentially drive the gate signal lines, the first voltage changing prior to driving successive gate signal lines. The gate driver includes a shift register for generating scanning signals to be applied respectively to the gate lines, wherein the shift register is responsive to a gate scanning clock; a level shifter making use of the first and second voltages to generate each voltage level of the scanning signals; and a voltage controller for changing the first voltage applied to the level shifter prior to disabling of the scanning signals. Preferably, a minimum value of the first voltage is higher than a maximum value of the second voltage.
According to one aspect of the present invention, the first voltage decreases prior to driving of the successive gate signal lines. In particular, the first voltage decreases exponentially, linearly or stepwisely.
According to another aspect of the present invention, the voltage controller includes a switch for cutting off the first voltage applied to the level shifter prior to disabling of the scanning signal; and a discharging path provided to the level shifter during period in which the scanning signal is cut off by means of the switch. The switch and the shift register respond to the gate scanning clock. The voltage controller may also include a timing controller for controlling the switch.
Alternatively, the voltage controller includes an input terminal for receiving the first voltage; a first resistor connected between the input terminal and an input port of the level shifter; a first control switch and a second resistor connected in series between the input port of the level shifter and a ground voltage line; and a second control switch connected in parallel to the first resistor, the second control switch being driven alternatively with the first control switch.
According to another aspect of the present invention, the voltage controller comprises a switch responsive to a gate output enable signal and is connected between the first voltage and the level shifter. Preferably, the gate output enable signal is inverse of the gate scanning clock.
A method of driving a liquid crystal display apparatus according to another aspect of the present invention includes the steps of inputting a first voltage and a periodically changing second voltage; supplying the second voltage, via a switching device, to the gate line; and supplying the first voltage, via the switching device, to the gate line, the switching device being controlled by the shift register, wherein a minimum value of the second voltage is higher than a maximum value of the first voltage.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.